1. Field of the Invention
The present invention relates to an integrated circuit layout design system, and method thereof, and program and, in particular, to a layout verification method for the layout design of semiconductor integrated circuits.
2. Description of the Prior Art
One example of the conventional semiconductor integrated circuit layout design technologies is shown in FIG. 15. Referring to FIG. 15, the system includes placement and routing means 1601, layout verification means 1602, an LVS (Layout Versus Schematic verification) rule file 1611, and a layout database 1612. The layout verification is carried out by following a procedure shown in the flowchart in FIG. 16.
Referring to FIG. 16, a mask layout of libraries such as basic logic gate cells, macro cells, and substrates is first created and only terminal geometries and wiring prohibited areas are extracted from the mask layout to generate a layout used by the placement and routing means 1601 (step 1). The mask layout of a library is verified by the layout verification means 1602 and, if no errors are found (step 2), then the layout is stored in the layout database 1612.
Then, cells are placed and wiring is provided between the cells by the placement and routing means 1601 (step 3). The placement and routing means 1601 performs design rule checks based on the layout for the placement and routing means and repeats rewiring until no error is found (step 4), and then outputs a mask layout resulting from the placement and wiring to the layout database 1612. The layout verification means 1602 retrieves from the layout database 1612 the libraries such as cell and substrate and the mask layout resulting from the placement and wiring and performs an LVS verification based on the LVS rule file 1611 (step 5). If an error is found, the library correction (step 1) or placement and wiring (step 3) are repeated until no errors are found (step 6). Then, the layout design is completed.
A technique for the LVS verification in layout design is disclosed in Japanese Patent Laid-Open No. 6-37183.
In the design process shown in FIG. 16 which is performed by the conventional layout design system shown in FIG. 15, the LVS verification is performed after wiring errors are eliminated. In the LVS verification, a larger number of variances between a layout and a schematic will decrease the precision of specifying erroneous portions and increase the number of erroneous outputs. At worst, it will become difficult to perform error analysis. Among other wiring errors, short circuits in wiring, are erroneous connections that do not conform to the schematic. Therefore, the LVS verification cannot be performed until the number of short circuits in wiring is adequately reduced.
If an error is found through the LVS verification, the conventional design process returns to the library creation step or placement and wiring step. Especially in design that involves development of a new library, the library design step and the placement and wiring step are performed concurrently and it is often the case that so many errors are detected in a mask layout of a library that the designers must go back to the library creation step to correct the library layout.
Thus, the conventional layout design systems have the problem that the LVS verification cannot be performed until the number of short circuits in wiring is sufficiently reduced and, if errors are detected in the LVS verification, designers must go back to the library creation step to correct the library, which can unexpectedly delay completion of the layout design at the last minute.
The technique described in Japanese Patent Laid-Open No. 6-37183 attempts to improve the efficiency of LVS error analysis by detecting certain types of LVS errors by means of a different verification means in an early stage to reduce the number of errors found in the LVS stage. In Japanese Patent Laid-Open No. 6-37183, however, no mention is made of wiring errors that can occur in the course of layout design. Therefore, also in the technique disclosed in Japanese Patent Laid-Open No. 6-37183, the LVS verification cannot be performed until the number of short circuits in wiring is adequately reduced. Thus, the problem stated above persists.
An object of the present invention is to provide an integrated circuit layout design system, and method thereof, and program, capable of enabling the LVS verification in an early stage of layout design.